new triacs with high commutation and dv/dt performances are now available on the market. generally these triacs are only triggerable in the 3 first quadrants (case of snubberless and logic level triacs) as shown in figure 1. this paper describes a trigger circuit supplying a negative gate current for quadrants ii and iii implemented in a system using a positive power supply. without a new design, just by adding a capacitor and a diode new w series triacs can replace conventional triac. i - principle : figure 2 shows the schematic of a system with a sensor, logic and positive power supply (with respect to the anode 1 of the triac). to drive the triac in the 2nd and 3rd quadrants a discharge capacitor is used as shown in figure 3. 1/ principle : - the transistor is switched off, capacitor c is charged through resistance r2 and diode d. the diode is used to avoid a capacitor load current through the gate of the triac. a schottky diode could be used to improve the voltage drop level lower than the gate non trigger voltage (v gd ). - when the triac is triggered, the transistor tr is switched on, c is discharged through r1 and tr and a negative current flows through the gate of the triac. the capacitor c acts as a differentiation. we have to consider different parameters to define all the components : - the gate trigger current of the triac (i gt ) - the time duration of the gate current - the latching current (i l ) especially for small or inductive loads. application note AN440/0592 for operation in quadrants i and iii triac drive circuit ? ph. rabier figure 1 : the quadrants of a w series triac. ++ not triggerable ig ia + 1 st 2 nd 3 rd 4 th 01phr160 figure 2 : synoptical diagram of a classical system. supply sensor logic trigger load line +v cc 02phr 160 figure 3 : basic diagram of the trigger. +vcc line r2 r1 snubberless triac d tr r3 load c 03phr 160 1/5
2/ review : dfinition of the latching current (i l ): the i l of a triac is the minimum value of the main current which allows the component to remain in the conducting state after the gate current i g has been removed. that is to say the gate current has to be higher than i gt until the main current reaches the latcing current. example : for the cw snubberless triac : q1 - q3 : i l max = 50 ma q2 : i l max = 80 ma with : gate pulse duration of 20 m sattj=25 c i l max is specified in the cw series triac data sheet. statistically, for bw series triacs we can use the k ratio k=i l max/i gt max k = 2,3 two solutions are possible : - triggering with a delay after zero voltage crossing such that the main current is higher than i l . - triggering at zero voltage crossing with a long discharge time in order to have no problem with i l . ii - the case with a resistive load : 1/ first solution: delayed pulse current (figure 4). the gate pulse is shown in figure 5 : t1 calculation : the triac has to be triggered when the main current is higher than the latching current, that is to say t1min is : t 1 = 1 w arcsin ? ? ? i l max i rms `` 2 ? ? ? where w =2. p . ? i rms : minimum rms current in the worst case (depending on line and load dispersion). the curve given shows the minimum time versus i rms current through the anode (figure 6). the gate current calculation : i gt is the maximum gate trigger current specified in the data sheet. to ensure a good safety margin and good triggering we have chosen i g = 2.i gt with a pulse duration t2 higher than 20 m s. figure 4 : triggering with delay t1 after zero crossing. anode current gate current 50ma/div 20ma/div 0.1ms/div 04phr160 figure 5 : gate pulse. ig t igm igm/2 t2 05phr160 figure 6 : t1 time versus i rms for different latching currents. ? application note 2/5
all the components can be defined by the following formulae : r1max = (v cc -v gk - vce)/(2.i gt ) with v gk =2vati g = 2.i gt cmin = t2/(r1.log2) with t2 = 20 m s r2max = 0,001/c curve 7 gives the minimum capacitance versus supply voltage for different sensitivity. in this way the rms current is lower than the full wave current, the rms current/full wave current ratio is : k 2 = 1 - 2 . t 1 t + 1 2 p . sin ( 4 p t 1 t ) the calculation gives for a 6 amps cw triac with a 2 amps sine current and with an il = 80 ma. t1 = 90 m s k = 0,99 that means the losses are lower than 1%. 2/ second solution : wide current pulse at zero crossing. it consists of triggering the triac at zero voltage crossing voltage as shown in figure 8. note : in figure 8, the pulse through the transistor base is cancelled before the capacitor is fully discharged to save energy. all the components can be defined by the following formulae : t 2 min = 1 w arcsin ? ? ? i l i rms `` 2 ? ? ? + 20 m s r1max = (v cc -v gk -v ce )/(2. ig t) cmin = t2/(r1.log2) r2max = 0,001/c in this way the rms current is equal to the full wave current. figure 7 : capacitance value versus supply voltage for different sensitivity. figure 8 : triggering at zero voltage. anode current 50ma/div gate current 20ma/div 0.2ms/div 08phr160 ? application note 3/5
3/ comparison between these two solutions : the calculation of all the components is shown iii - case of inductive load : with an inductive load another problem occurs : the problem of the phase lag between load current and load voltage. it can be solved by taking into account : - the maximum phase lag to define a delay time td. - the latching current to define the time t1 - the inductance to define the time t2= v/l at the moment when the triac is fired (t2 > 20 m s) to have an anode current higher than the latching current i l . the figure 10 shows the anode current and the gate current in the triac, is the case of an inductive load. in the following table for 3 differents cases if the phase lag is not constant a gate pulse train can be used, the calculation parameters are the same, except for r2 : the capacitor c has to be charged between 2 pulses so the equation is : r2=(time between 2 pulses)/(5xc) iv - the case of a small load : this trigger circuit can not be effectively used to drive small loads (like valves, fan etc...) because the latching current value is not very small compared to the load current. in this case a dc gate current is needed. v - conclusion : in the case of controllers supplied by positive voltage this solution allows of the replacement of conventional triacs used in the 1st and 4th quadrants by snubberless or logic level triacs triggerable only in the 3 first quadrants without a new design but only by adding a capacitor and a diode. two configurations are possible : first solution : triggering after the zero voltage crossing. advantage : capacitor value lower than 1 m f. disadvantage : the need to have a delay after the zero voltage crossing (delay system needed). second solution : triggering at zero voltage crossing. advantage : 100% of the power used in the load. disadvantage : capacitor value of a few microfarads. i rms =5a v cc =10v i rms =2a v cc =5v i rms =5a v cc =5v with delay at zero crossing with delay at zero crossing with delay at zero crossing t1 min ( m s) 36 0 91 0 36 0 t2 min ( m s) 20 56 20 111 20 56 r1 max ( w ) 105 105 34 34 34 34 c min ( m f) 0.275 0.77 0.85 4.7 0.85 2.37 r2 max ( w ) 3.7 1.3 1.18 0.212 1.18 0.42 figure 9 : component values for 3 differents cases : triac used : bta08-600cw (i gt = 35 ma) figure 10 : current through an inductive load. line voltage anode current ig igt 2igt il t t td t1 t2 10phr160 ? application note 4/5
with inductive loads (motor, transformer, etc...) a pulse train can be used because of the phase lag between current and voltage. with small loads (valve, fan,...) a dc gate current has to be used to drive the triac because of the latching current. in case of logic or transistor failure, the capacitor c operates as an open circuit for dc current and avoids all triggering. this factor acts as a safety feature. information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-tho mson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - printed in italy - all rights reserved. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. ? application note 5/5
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